#include <stdatomic.h>
uint32_t g_4 = 1;
int32_t g_36 = 0;
atomic_char a_72 = ATOMIC_VAR_INIT (0);

void main () {
  if (g_4) {
  } else
    g_36 = 0;
  atomic_load_explicit (&a_72, 0);
  g_36 = 0;
}

The reference trace for main is:

     g_4   1  4   Init
     g_36  0  4   Init
     a_72  0  1   Init
RaW* g_4   1  4   Load
     a_72  0  1   ALoad
WaW* g_36  0  4   Store

The trace generated by gcc --param allow-store-data-races=0 -O2 (or -O3) is:

     g_4   1  4   Init
     g_36  0  4   Init
     a_72  0  1   Init
     g_4   1  4   Load
     g_36  0  4   Store
IR * a_72  0  1   ALoad
     g_36  0  4   Store

The optimiser introduced the idempotent store Store g_36 0 4, which cannot be observed by a non-racy context. The optimised assembly code that inserts the store is:

    movl    g_4(%rip), %edx
    xorl    %eax, %eax
    testl   %edx, %edx
    cmovne  g_36(%rip), %eax
    movl    %eax, g_36(%rip)

As in the s1 example, it is unclear if it is a good idea to let a compiler introduce indempotent writes.

Current status: not yet reported.

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