Hardware designs typically combine parallelism and resource-sharing;
a circuit's correctness relies on shared resources being accessed
mutually exclusively.
Conventional high-level synthesis systems guarantee mutual exclusion
by statically serialising access to shared resources during a
compile-time process called scheduling.
This approach suffers from two problems:
(i) there is a large class of practical designs which cannot
be scheduled statically; and (ii) a statically
fixed schedule removes some opportunities for parallelism leading to
less efficient circuits.
This paper surveys the expressivity of current scheduling methods and
presents a new approach which alleviates
the above problems: first scheduling logic is automatically generated to
resolve contention for shared resources dynamically;
then static analysis techniques remove redundant scheduling logic.
We call our method Soft Scheduling to highlight the analogy with
Soft Typing: the aim is to retain the flexibility of dynamic scheduling
whilst using static analysis to remove as many dynamic checks as possible.
